The present invention relates to an integrated memory having memory cells with a magnetoresistive storage property. The memory cells are in each case connected between one of a plurality of column lines and one of a plurality of row lines. The invention also relates to a method of operating such a memory.
Memory cells with a magnetoresistive storage effect generally have variable-state ferromagnetic layers for storing data signals. This storage effect is generally referred to as the GMR (giant magnetoresistive) effect or TMR (tunneling magnetoresistive) effect. In this case, the electrical resistance of such a memory cell is dependent on the magnetization of the ferromagnetic layers.
Integrated memories having memory cells of this type, also referred to as MRAMs (Magnetoresistive Random Access Memory), are often of a similar structure to that of, for example, integrated memories of the DRAM (Dynamic Random Access Memory) type. Memories of this type generally have a memory cell configuration with row lines and column lines which run essentially parallel to one another, with the row lines usually running transversely with respect to the column lines.
A MRAM memory of this type is known from International Publication No. WO 99/14760. There, the memory cells are connected in each case between one of the row lines and one of the column lines and are electrically connected to the respective column line and row line. The memory cells with a magnetoresistive storage effect have in this case a higher impedance than the row lines and column lines. The row lines are in each case connected to a terminal for a selection signal for reading a data signal of one of the memory cells via the column line connected to the memory cell. For the reading of a data signal of one of the memory cells, the column lines are connected to a sense amplifier. For reading, the current which can be detected on the column line is measured.
In the case of a MRAM memory of this type, there are no diodes or transistors to connect the memory cells to the respective column line for reading or writing a data signal in response to being addressed. This achieves advantages, in particular in terms of the geometrical configuration of the memory cells.
For a properly conducted reading operation, it is important that all the column lines and row lines apart from the selected row line are at the same potential. If, for example, the potentials differ between the column line to be read from and a column line that has not been selected, the current to be detected is superposed by parasitic currents which arise due to a difference in potential on the column line to be read from. This may lead to a defective reading operation in respect of the memory cell to be read from.
The row lines are generally connected to row line drivers, so that the row lines are at a predetermined potential. The column lines have a corresponding potential applied to them via corresponding sense amplifiers. In particular in the case of spatially distributed configurations of row line drivers and sense amplifiers along the memory cell array of the integrated memory, it is comparatively difficult to configure and operate the row line drivers and sense amplifiers in such a way that the corresponding column lines and row lines are in each case at exactly the same potential.
It is accordingly an object of the invention to provide an integrated memory with a magnetoresistive storage effect which overcomes the above-mentioned disadvantages of the heretofore-known integrated memories of this general type and which allows a comparatively reliable reading of one of the memory cells.
It is also an object of the present invention to provide a method of operating such an integrated memory that allows a comparatively reliable reading operation for one of the memory cells.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, including:
a plurality of column lines;
a plurality of row lines;
a plurality of memory cells each connected between a respective one of the column lines and a respective one of the row lines, the memory cells having a magnetoresistive storage property;
a terminal for providing a selection signal;
a selection circuit connected to the row lines such that in each case one of the row lines is connectable, in the selection circuit, to the terminal in order to read a data signal from one of the memory cells connected to the one of the row lines; and
a control device operatively connected to the selection circuit and controlling the selection circuit such that given ones of the row lines not connected to the one of the memory cells are electrically isolated in the selection circuit for reading the data signal.
In other words, the object of the invention concerning the integrated memory is achieved by an integrated memory of the type described above in which the row lines are connected to a selection circuit, in which one of the row lines in each case can be connected in the selection circuit to a terminal for a selection signal for reading a data signal of a memory cell connected to the row line and in which the selection circuit is configured and can be driven by control device in such a way that the row lines not connected to the memory cell are electrically isolated in the selection circuit for the reading of the data signal.
With the objects of the invention in view there is also provided, a method of operating an integrated memory, the method includes the steps of:
providing memory cells having a magnetoresistive storage property, the memory cells being connected in each case between one of a plurality of column lines and one of a plurality of row lines;
connecting, during a reading operation, one of the row lines in a selection circuit to a terminal for a selection signal and reading a data signal of one of the memory cells connected to the one of the row lines; and
electrically isolating those row lines, which are not connected to the one of the memory cells, in the selection circuit during the reading operation.
In other words, the object of the invention concerning the method is achieved by a method of operating an integrated memory of the type described above in which, during a reading operation, one of the row lines is connected in a selection circuit to a terminal for a selection signal and a reading of a data signal of a memory cell connected to the row line takes place, and in which the row lines not connected to the memory cell are electrically isolated in the selection circuit during the reading operation.
The integrated memory according to the invention and the method of operating an integrated memory according to the invention make it possible to avoid parasitic currents during the reading of a data signal of one of the memory cells. This is achieved by the row lines that have not been selected being driven in such a way that they are electrically isolated in the selection circuit during the reading. These row lines accordingly have a kind of floating state and can be brought to a uniform potential. The avoidance of parasitic currents allows a comparatively reliable reading of the data signal, since the current to be detected, on the basis of which conclusions are drawn with respect to the information stored in the memory cell, is not superposed or falsified by parasitic currents.
In one embodiment of the memory according to the invention, the row lines are in each case connected to a driver circuit which can be operated in a conducting state or in a nonconducting state. These driver circuits can be used to drive nonselected row lines in such a way that they are electrically isolated for the reading of the data signal. For this purpose, the driver circuits are operated in the nonconducting state. The respective driver circuit has, for example, switching devices in the form of transistors which are connected to the respective row line via their source-drain paths. These transistors are operated in a corresponding nonconducting state.
In one embodiment of the method according to the invention, the row lines are precharged to a common precharging potential. The precharging is followed by reading of the data signal. This may take place by using a suitable precharging device of the memory. In this way it can be ensured that the floating row lines are at a common potential directly before the respective reading of a data signal. In this case, the reading of the data signal is preferably delayed until the respective potential profiles on the row lines are in a static state.
In a further embodiment of the invention, the row lines are precharged via at least one of the column lines. In this case, it is advantageous to precharge the row lines via all the column lines. The row lines are in this case charged via the respective memory cells to the potential of the respective column lines. Since the memory cells have a resistance characteristic, it is ensured that the row lines assume exactly the potential of the column lines when a static state is achieved. This achieves the overall effect that all the nonselected row lines and the column lines are at the same potential directly before reading.
In an other embodiment of the invention, the column lines are precharged by a sense amplifier, which also serves for the reading of a data signal of a selected memory cell. The sense amplifier is connected to the corresponding column line for the reading of the data signal. The precharging of the column lines or the row lines by one or more sense amplifiers is carried out before the respective reading. For this purpose, the respective sense amplifier is configured as a suitable precharging device. The time period until potential equalization between the column lines and row lines is achieved is not significant, since rapid potential equalization can be achieved between the column lines and one of the row lines by the parallel connection of the memory cells.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory having memory cells with a magnetoresistive storage effect and a method of operating such a memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.